1. Field of the Invention
The invention relates generally to a method of manufacturing semiconductor devices and, more particularly, to a method for forming dielectric isolation regions on an integrated circuit semiconductor die for isolation of adjacent devices, and integrated circuits produced thereby.
2. Description of the Prior Art
In the manufacture of high density integrated circuits, individual device structures are physically separated and electrically isolated from each other by an isolation region. Increasing integrated circuit complexity and speeds require increasing the number of devices on a single die of a given size (i.e., the device density). Consequently, physical spacing between devices decreases.
Processes for forming isolation regions fall generally into two major categories. The first category encompasses all of the variations of LOCOS (Local Oxidation of Silicon) and involves exposing silicon to a heated oxidizing atmosphere to form silicon oxide. Masking the active regions to prevent oxidation permits subsequent fabrication of active device structures within those masked regions. The second category includes the various trench forming and filling isolation structures. These structures require etching a portion of the substrate and then filling the etched portion with a dielectric material.
LOCOS methods take advantage of the fact that silicon nitride can provide a thermal oxidation mask for silicon. A silicon nitride layer is patterned to expose portions of an underlying silicon substrate. When the substrate is exposed to an oxidizing atmosphere, silicon oxide is formed in the exposed portions while no oxide is formed in the unexposed portions.
Despite their broad application, LOCOS based processes have several drawbacks. First, the thermally grown oxide has approximately twice the thickness of the silicon consumed in the thermal oxidation process. Consequently, the resulting structure is non-planar.
Second, typically the silicon oxide intrudes laterally under the edge of the nitride mask. The nitride layer is pushed-up and an irregularly shaped oxide defect, called a "Bird's Beak" is formed. As the "Bird's Beak" extends into the unexposed region, the area in which devices can be built is reduced. In addition, the formation of "Bird's Beak" regions creates stress in the silicon substrate.
Finally, the various LOCOS processes suffer from oxide thinning. That is, the thickness of the oxide film grown in any specific isolation region decreases with decreasing isolation width. For example, a field oxide that is grown to a thickness of 400 nm (nanometers) above a 1.5 .mu.m wide isolation region will be only 290 nm thick above a 0.8 .mu.m isolation region, a reduction in thickness of more than 25%. In 0.2 .mu.m isolation windows the thinning effect can be as large as 80%. Thus, the thickness of the isolation oxide formed can vary within a device.
These drawbacks serve to severely limit the usefulness of LOCOS-based isolation for semiconductor devices. As a result, recent efforts have focused on trench isolation and in particular shallow trench isolation (STI) for semiconductor integrated circuits employing deep sub-micron design rules. STI eliminates two major problems of LOCOS type isolation schemes. First is the intrusion into active areas by the LOCOS "Bird's Beak". Thus, absent a "Bird's Beak" region, STI allows for smaller isolation spacing than that possible with LOCOS processes. In addition, as STI involves filling a photolithographically defined trench region with a dielectric material, oxide thinning is eliminated. Thus, STI allows for isolation regions of varying widths to be fabricated within a single circuit. However, STI process and structures have other drawbacks that limit their acceptance and usefulness for devices employing sub-micron design rules. Among these other drawbacks are the increased process complexity required to create such STI regions, inversion of vertical trench sidewalls of P-type active areas, less than adequate planarity of the resulting surface, and stress induced by trench etching processes and by trench fill materials.
Therefore, improved methods of forming isolation regions are needed for semiconductor devices that will reduce and/or eliminate the effects of the problems associated with LOCOS or STI methods. In addition, these improved methods should result in a device structure with enhanced planarity. Improved methods, and structures thereof, are also needed that reduce or eliminate parasitic leakage and capacitance in such deep sub-micron semiconductor devices. Finally, the improved methods, and structures thereof, should provide reduced process complexity and manufacturing costs while resulting in increased device yields.